1. Field of the Invention
The invention relates generally to compositions, structures and devices for silicon-on-insulator (SOI) compositions, devices and applications, and more particularly to compositions, structures and devices utilizing substantially single crystal compositions for SOI compositions, devices and applications.
2. Description of the Related Art
It is well known that pure crystal or single-crystal rare-earth oxides (REOx), rare-earth nitrides (REN) and rare-earth phosphides (REP) do not occur in nature, nor can they be grown using prior-art growth techniques. For this reason, single crystalline oxides, nitrides and phosphides compatible and functionalized for use with ultra large scale integrated (USLI) silicon electronics processing has to date eluded the silicon electronics industry. In contrast, amorphous oxides are comparatively straightforward to realize. Modern silicon electronics owes a large part of the enormous success to the robust native oxide of silicon, that is, stoichiometric silicon dioxide (SiO.sub.2). The crystalline Si and amorphous SiO.sub.2 interface can be prepared as an almost perfect defect free interface. The high quality of the Si/SiO.sub.2 interface is difficult to replicate in practically any other material system.
This inability to create single-crystal oxides affects three major application areas as recited hereafter.
Future ULSI technology node scaling into the deep sub-micron regime requires ultrathin gate oxides of SiO.sub.2 for use in field effect transistors (FETs) to be of the order of 1-10 nanometers in thickness. Unfortunately, fundamental physics problems at such small SiO.sub.2 thickness appear: (i) large quantum mechanical tunneling gate current; (ii) dielectric breakdown; and (iii) reliability degradation. These problems require alternate gate materials, (such as higher dielectric constant oxides) and modified Si substrates, such as silicon-on-insulator (SOI), to be introduced into ULSI technology nodes.
Complementary to the Si electronics industry is the demand for semiconductor materials which are optically active and compatible with Si processing technology. To date there does not exist a clear answer to this Si industry compatibility issue for optoelectronic materials. Efficient and inexpensive electrically driven planar photonic Si-based devices operating at fiber communications wavelengths are the driving rationale for solving optoelectronic integration with mainstream Si electronics. One path toward such a goal is the creation of a material that can be relatively easily fabricated and integrated with Si-based ULSI electronics manufacturing. This philosophy is a potential solution for reducing optoelectronic system manufacturing costs. Further, optoelectronic emitters and absorbers operating at 1.5 micron wavelengths that are readily integrable with silicon electronics offer an explosive increase in functionality and reduction in cost/function. Using the present invention, active and passive photonic elements can be integrated along side, above or beneath planar complementary metal oxide semiconductor (CMOS) electronics. For example, U.S. Pat. No. 6,734,453, describes how a single crystal photonic layer can be buried beneath an active CMOS layer. This approach allows the photonic and electronic layers to be separately optimized. Furthermore, silicon-based rare-earth containing multi-layers are disclosed.
Finally, there is also a demand for higher density and function magnetic storage materials. Simplistically, a magnetic media which can be processed using ULSI tools is of great interest. However, once again a clear answer does not presently exist. The present invention allows the use of high densities of magnetic rare-earth ions in a single crystal form. The utility of the said magnetic single crystal, for example single crystal rare-earth oxide, is that can be: (i) deposited as a thin film compatible with silicon; and (ii) the possibility of using silicon microelectronics for electrical read/write access for the storage of information using the intrinsic properties of the confined magnetic ions.
There are primarily two critical mainstream Si electronics issues in areas of ULSI FET gate oxides and silicon-on-insulator materials. The two areas have been historically separate concerns and are elegantly related for the first time using present invention. The present invention potentially solves both areas individually and/or allows an integrated approach by virtue of the unique fact the present invention is: (i) single crystal; (ii) a high-k dielectric; (iii) commensurate with and may be epitaxially deposited with substantially single crystal silicon; and further (iv) multilayers of single crystal silicon and single crystal rare-earth oxides may be deposited at will.
A possible solution to the USLI gate oxide problem, is the substitution of SiO.sub.2 with a material of higher dielectric constant, so-called “high-k dielectrics”. A possible short-term dielectric material is the incorporation of nitrogen in SiO.sub.2 to form silicon oxynitride (SiO.sub.xN.sub.y). Possible candidate long term high-k solutions are oxides of titanium oxide (TiO.sub.2), tantalum pentoxide (Ta.sub.2O.sub.5), halfnium oxide (HfO.sub.2), zirconium oxide (ZrO.sub.2) and aluminum oxide Al.sub.2O.sub.3. Alloys and/or combinations of the above materials may also prove effective in leveraging advantageous features of each high-k binary oxide, such as HfZrO.sub.4. Similarly, high-k binary oxides combined with SiO.sub.2 or Si, such as zircon HfSiO.sub.4 or HfSiO.sub.2, may also prove to be effective gate oxides.
However, to date all such alternative gate oxide candidates mentioned above fail in one or more areas of required device performance.
These areas include (i) bulk gate material quality; (ii) silicon/gate oxide interface quality; (iii) gate material conduction and valence band offsets with respect to bulk Si; (iv) breakdown strength; (v) gate oxide band gap; and (vi) growth technique. Further, practically all technologically relevant oxides investigated as possible replacement gate materials to date are either amorphous or at best polycrystalline. Worthy of note is the perovskite-like crystal, strontium titanate, SrTiO.sub.3 (STO). This particular compound can be grown with limited thickness as a single crystal on Si(001)-oriented wafers. However, crystallinity in this case is not sufficient criterion for FET gate oxide suitability. Unfortunately, the silicon/STO hetero-junction offset is almost entirely located in the valence band- and therefore is unsuited to Si-based ULSI FET devices.
One current growth technique for precise ultrathin oxide layer deposition is a variant of well established chemical vapor deposition (CVD) techniques. Gate oxide layer thickness of the order 1-10 nanometers (nm) requires a complex pulsed reactive hydride and chloride precursor gas based deposition/purge cycle CVD process based on U.S. Pat. No. 4,058,430—presently termed atomic layer deposition (ALD). Recent success of the ALD process for demonstration of ultrathin oxides mentioned above, unfortunately neglects specific problems related to practical ULSI device issues:
Central to the inadequacy of SiO.sub.2 as a viable ultrathin gate oxide is the presence of impurities, primarily those related to hydrogen, which are responsible for premature failure and low breakdown voltages in ULSI devices. Therefore, it is unclear how hydride and chloride based precursor ALD solves this issue.
The issue of interface quality is typically not addressed, that is, the interfacial quality of bulk Si/high-k oxide. Typically, the interfacial quality and/or defect density is inferior to that of the Si/SiO.sub.2 system and therefore FET channel and threshold voltage performance is compromised.
The important issue of electron confinement is understated in the pursuit of high-k gate dielectrics. Of central importance is the energy barrier presented to electrons and holes at the interface between two dissimilar semiconductors, namely, the gate oxide and bulk Si, hereafter referred to as a hetero-junction. The hetero-junction conduction band offset between the high-k oxide and bulk Si is typically less than the SiO.sub.2/Si system. Therefore, thermionic emission of electrons across the potential barrier is greater in the Si/high-k heterojunction.
Regardless of the final ULSI implementation of high-k gate oxide(s), silicon-on-insulator (SOI) substrates are a key technology for high performance ULSI. To date, practical implementation of SOI substrates can be classed as the following forms, (i) a thin single crystalline silicon layer separated from the silicon bulk substrate by an amorphous SiO.sub.2 layer, forming the insulator and (ii) a thin layer of re-crystallized or deposited Si onto a glass or wide bandgap substrate, such as sapphire. Both forms are required to exhibit: (i) high quality single crystal Si surface active layer; (ii) high uniformity and a low defect density active Si layer, and (iii) a high uniformity and low leakage insulator.
The first form of SOI conceptually consists of a thin silicon active layer upon a SiO.sub.2 buried oxide (BOX) insulator layer substantially disposed across a bulk Si substrate. The BOX layer is typically formed using two fabrication methods. One method uses primarily high energy oxygen implantation through the surface of the silicon to an appropriate depth and profile, followed by an aggressive thermal anneal processes in order to recrystallize the surface damaged active Si layer to single crystal Si. This technique is known as the separation by implantation of oxygen process (SIMOX). Another method uses substantially wafer bonding of two separately oxidized silicon wafer surfaces that are brought into intimate contact and annealed to form a BOX layer. Once the two substrates have been joined, one of the silicon substrates in then physically reduced in thickness in a direction from one of the exterior silicon surfaces toward the BOX layer. This is achieved by chemical mechanical polishing (CMP) and or etching, or via physical abrasion down to the active Si layer thickness required. A variant on the wafer bonding approach is to use atomic layer cleaving, via hydrogen implantation of a buried defect layer. Upon annealing the hydrogen forms a preferential cleaving plane and a large portion of the sacrificial silicon substrate can be removed.
However, extensive CMP is still required to form a uniform flat active silicon layer surface. Both forms of SOI, however, share the unfavorable properties that the Si/buried oxide interface is highly defective and is not usable as a lower gate dielectric layer for FET devices. Secondly, both forms of SOI are presently costly to produce and it is this fact that hinders wider acceptance of SOI technology in present and future ULSI processes. Thirdly, conventional SOI fabrication technologies are time consuming and physically require many serial processing and cleaning steps. Fourthly, active Si layer thickness required for fully depleted SOI, typically less than or equal to 500 Angstroms, are extremely difficult to realize. Finally, the BOX thickness is required to be relatively thin.
To date general deposition techniques have been used to explore RE-oxide thin films on Si substrates. In one method, light rare earth metals, occurring at the beginning of the rare-earth sequence in the periodic table of elements, have been utilized. Light metal rare-earth oxides have been demonstrated by electron-beam evaporation (EBE) of a single stoichiometric RE-oxide target. The disadvantage of this technique is stoichiometry of the target does not ensure stoichiometry of the resulting deposited thin film oxide. Most notable prior art using EBE are Y.sub.2O.sub.3, Pr.sub.2O.sub.3 and Gd.sub.2O.sub.3 thin films.
Y.sub.2O.sub.3 and Pr.sub.2O.sub.3 have been deposited on silicon substrates and are predominately polycrystalline and or amorphous in nature when deposited on Si(001) oriented substrates. Single crystal thin films have not been demonstrated on Si(001)-oriented substrates.
A further disadvantage of this technique is that prolonged use of the single source EBE rare-earth oxide results in unfavorable rare-earth-to-oxygen ratio variation. Yet another disadvantage of this technique is the lack of evaporant flux control by virtue of the EBE process. Yet a further disadvantage of this technique is the introduction of charged species/defects that affect trapped oxide charge in an unfavorable manner. The later point is crucial to the performance of FET devices.
In a second method, the deposition of light rare-earth metal oxides is achieved using high vacuum environment deposition, unexcited molecular oxygen gas and EBE of elemental light rare-earths. An example of this method is found in U.S. Pat. No. 6,610,548, which describes a two source deposition technique using vacuum EBE of Cerium rare-earth source material and unexcited molecular oxygen gas. Disclosed are cerium dioxide CeO.sub.2 rare earth oxide layers grown on Si substrates at growth temperatures ranging 100<T.sub.growth<300 deg C.
It has been known for well-over a decade that clean (001)-oriented surfaces of Si and Ge exhibit 2.times.1 reconstructions. Using typical surface analysis tools in a suitable environment, (such as reflection high energy diffraction, i.e.: RHEED, and high vacuum conditions), two 2.times.1 reconstructions rotated by 90.degree. are typically observed when the native SiO.sub.2 oxide is removed. An ideal Si surface of a diamond lattice structure represents an non-terminated Si (001)-oriented surface. Each face Si atom will have two dangling bonds. The 2.times.1 reconstruction is due to a minimization of surface energy and a pairing of atoms in neighboring rows occurs, i.e., dimerization. Two orthogonally oriented 2.times.1 domains which are typically observed can be understood as dimers on terraces which are separated by single atomic layer steps of height equal to one quarter the bulk Si crystal lattice constant. RHEED diffraction patterns which show one 2.times.1 domain only, should then be observed in samples which exhibit ether (i) no steps or (ii) bi-layer steps of height equal to half the bulk Si lattice constant.
Single-domain Si(001) surfaces are easily obtained by preparing a Si surface which are intentionally misoriented from the ideal Si(001)-orientation. Typically, miscut substrates of approximately 1 to 6 degrees misoriented towards [110] can be used for this purpose.
U.S. Pat. No. 6,610,548 discloses the growth of amorphous and or polycrystalline growth of cerium dioxide on Si(001)-oriented substrates with a mixed 2.times.1 and 1.times.2 prepared surface. Following an oxide deposition is a high temperature anneal for recrystallization of the light rare-earth oxide, so that the crystal quality can be improved. The presence of initial amorphous silicon oxide and or amorphous cerium oxide initial layers in the growth sequence toward a final polycrystalline cerium oxide layer is completely different to the behavior observed in the present invention using technique 4, discussed later.
A major disadvantage of aforementioned techniques, as discussed in U.S. Pat. No. 6,610,458, is the limitation to the type of rare-earth oxide that can be used. Cubic structure crystallizations of rare-earth oxides of the formula REO.sub.2 are accessible, in general, to only the lighter rare-earth metals. The present invention teaches that beyond Ce, as the atomic number increases, most energetically favorable crystallizations are of the formula RE.sub.2O.sub.3. If fact, cubic rare-earth crystals will have significant net charge defect due to the multiplicity of rare-earth oxide oxidation state-thereby rendering such oxides inapplicable to high performance FET devices. Annealing such structures will result in mixed crystal phases, that is, polycrystallinity.
In a third method, a form of chemical vapor deposition is employed using molecular metal-organic precursors. Thin films of RE-oxides have been deposited on Si substrates by using a pyrolysis method. In this method thin organic films can be deposited using rare-earth metal which is attached to an acetylacetonate complex, namely RE(CH.sub.3COCHCOCH.sub-0.3).sub.3H.sub.2O, and evaporated under medium vacuum conditions (>10.sup.−6 torr) in a tungsten crucible. The resultant films are similarly plagued by amorphous and or polycrystal RE-oxide phases. The same arguments outlined in the introduction of this paper, relating to precursor ALD process, also holds for this metal-organic deposition technique.
Erbium oxide has been deposited on Si substrates using medium vacuum level electron-beam evaporation of a single Er.sub.2O.sub.3 target material and high pressure metalorganic chemical vapor deposition (MOCVD) using a precursor of tris(2,4-pentadionato) (1,100-phenanthroline) erbium(III) [Er(pd).sub.3.Phen. The deposited thin film material quality in both of the above growth methods, namely EBE and MOCVD, exhibited amorphous phases of erbium oxide and at best poorly polycrystalline material. Single crystal erbium-oxide films has not been demonstrated and or claimed as beneficial in prior art. Similarly, single crystal rare-earth oxide and silicon multilayers have not been demonstrated.
In summary, using EBE of a chemically stoichiometric rare-earth oxide single target or rare-earth organic precursor, in general, does not ensure the correct deposited film stoichiometry. This results in amorphous and or polycrystalline rare-earth oxide thin film. Departure from stoichiometry in the film deposition structure results generally in strongly disordered structures.
Accordingly, there is a need for improved silicon-on-insulator (SOI) compositions, devices and applications. There is a further need for substantially single crystal SOI compositions, devices and applications.